In this work, physical models of resistivity-size scaling and temperature effects in nanoscale copper interconnects are explored. Interconnects are a vital component of microprocessors, connecting elements within them. As microprocessors scale down in size, interconnects must also shrink. With decreasing size, the resistivity of interconnects becomes prohibitive to latency. As a result, analyzing an interconnect’s resistivity at advanced technology nodes is important. Electron scatterings from phonons, grain boundaries and sidewalls are used in a model of resistivity versus interconnect size. Grain boundary scatterings are modeled using a reflectivity parameter R ranging from ideal case R=0 of no electron reflection at a grain boundary to the worst case, R=1 where all electrons are reflected. Sidewall scattering contributions include sidewall roughness approximated to a sinusoidal form and use a different specularity parameter p, which is dependent on the liner material used. Tantalum, modeled as non-conducting, and graphene, which is conducting, are considered as liner materials. To model temperature effects on resistivity, the Bloch-Gruneisen formula is used to model electron-phonon scattering. Our work shows that for a smooth interconnect of cross-sectional area 800 nm² and aspect ratio 2, as R increases from 0.25 to 0.75, resistance per unit length increases from 5.07E-2 to 2.77E-1 Ohm/nm. As p increases from 0.25 to 0.75, resistance per unit length decreases from 3.21E-2 Ohm/nm to 1.07E-2 Ohm/nm for the same size. At the same dimensions, when surface roughness of 2 nm is added it accounts for 1.10% of the total resistivity. Roughness accounts for 15% of total resistivity when it is at 35% of total linewidth. We also discuss the role of topological metals in replacing copper as interconnects. Our work sheds light on the physics behind resistivity-size scaling in interconnects and can be used for interconnect design, optimization, and benchmarking at advanced technology nodes.